A. Technical Field
The present invention relates generally to the field of semiconductor wafer fabrication, and more particularly, to chemical mechanical planarization or polishing (CMP) of wafers.
B. Background of the Invention
The manufacturing of semiconductor devices, including integrated circuits, microchips, or chips, often involves multiple processes. For example, a semiconductor device may comprise a substrate on which a number of films of various chemical compositions are layered. During manufacturing, a layer's thickness or uniformity may need to be within a set limit for the final device to function properly. Thus, at one or more times during the manufacturing of a semiconductor device, the wafer under development may need to be planarized. One method for planarizing substrates utilized in semiconductor manufacturing is called chemical mechanical polishing or planarization. Chemical mechanical polishing or planarization (CMP) is a polishing process that uses a combination of mechanical removal and chemical etching to planarize a wafer's surface.
A typical CMP apparatus comprises a polish head (also referred to as a carrier head) and a polishing pad. The polish head is a tool fixture that holds a wafer during the CMP process. Typically, the wafer is held in place, in an inverted position, against the polish head through vacuum pressure. A polishing pad faces the wafer when the wafer is positioned on the polish head. During a CMP process, the polish head presses the wafer against the polishing pad. Depending on the particular CMP apparatus configuration, both the polishing pad and the polish head may rotate to create the mechanical polishing. Typically, a chemical etching solution is continuously pumped onto the polishing pad during the CMP process.
The chemical etching solution, also referred to as the “slurry,” is normally a mixture of an abrasive or abrasives and other chemicals. For example, a slurry may contain silica or alumina particles dispersed and suspended in an acidic or a basic etching solution, depending on the application.
CMP processes are normally used to planarize silicon wafers at both post-ingot wafer slicing and at various levels of the chip development. For example, once the bare silicon wafer is cut from the silicon ingot, its surface is usually rough and uneven. Generally, there are strict tolerances as to the planarity of the wafer before it can be used to produce yielding chips. To achieve an acceptable level of planarity, CMP is typically employed to planarize the wafer.
Also, during the production of an integrated circuit, it is typically very desirable that the wafer's surface be planar throughout each process. However, due to the nature of certain processes, a non-planar surface may be produced. This non-planar surface may lead to various problems in production, which generally leads to a reduced yield of functional chips. For example, due to uneven topography of the wafer, possibly resulting from prior deposition cycles or other manufacturing processes, reactants may grow uneven layers onto the surface of the wafer. Once again, CMP is often used to reduce the wafer's altitude variations so that subsequent process steps can be performed.
Although the use of CMP processing during the manufacturing of semiconductor manufacturing helps increase yield, the CMP process has limits. Currently, the CMP process may not be able to planarize sufficiently a wafer that possesses too great a disparity in wafer surface altitude. Furthermore, current CMP process may introduce defects into wafers by over-polishing or under-polishing certain areas. These problems may lead to decreased yields of semiconductor products.